1. Field of the Invention
The present invention relates to a process for producing a semi-insulating compound semiconductor used in electronic devices, for example, OEICs (i.e., optoelectronic IC), HEMTs (i.e., high electron mobility transistor), ion implanted FETs (i.e., field effect transistor) or the like, in particular, to a technique to semi-insulate a compound semiconductor by a heat-treatment.
2. Description of Related Art
For making a III-V compound semiconductor crystal including Si or S as shallow donors, high-resistive, i.e., semi-insulative, to have a resistivity of not less than 10.sup.6 .OMEGA..multidot.cm, a process of adding Fe, Co, Cr or the like as deep acceptors to the crystal has been industrially used. The semi-insulation is based on a mechanism in which deep acceptors compensate shallow donors. Therefore, it has been believed that the added amount of an element which acts as a deep acceptor must be larger than the content of shallow donors in the crystal in order to semi-insulate the crystal.
However, the amount of Fe, Co, Cr or the like doping the compound semiconductor crystals for semi-insulation is preferred to be as small as possible. The reason of this is that Fe, Co, Cr and the like serve as deep acceptors in ion implanted electronic devices, e.g., an FET, and they reduce the activation efficiency of ion implanted donor-type impurities therein. In the case of devices operating at high frequencies such as an OEIC, HEMT or the like, these elements such as Fe, Co, Cr and the like diffuse in the epitaxial layers, trap carriers, and deteriorate high-frequency and high-speed performances. In addition, these elements such as Fe and the like easily segregate so that the concentrations thereof differ in upper and lower portions of the compound semiconductor crystals, resulting in the nonuniformity of activation efficiency of implanted ion over the crystal, and therefore resulting in low yields of electronic devices based on these substrates.
Conventionally, for example, Fe doped InP single crystals have been used for semi-insulating InP single crystal substrates. When the concentration of Fe or the like in InP single crystal is less than 0.2 ppmw, the resistivity is reduced to below 10.sup.6 .OMEGA..multidot.cm and the semi-insulation deteriorates. In order to obtain semi-insulating crystals, Fe or the like had to be doped with more than a predetermined concentration, that is, not less than 0.2 ppmw. Generally, it has been believed that a reduced concentration of Fe, Cr and the like in the III-V compound semiconductor reduces the resistivity of the compound semiconductor because the concentration of the impurity elements, i.e., residual impurity, providing a shallow donor amounts to a level of reduced concentration of all of the Fe, Cr and the like. However, the present inventors proposed that electrically active point defects, as well as the compensation by shallow donors and deep acceptors related to impurity atoms, respectively, characterize the mechanism of semi-insulating the InP single crystal and diligently studied to discover that controlling the concentration of the point defect by means of heat-treating the single crystal caused even a much lower concentration of impurity element providing deep acceptors than a conventional concentration thereof so as to semi-insulate the III-V compound semiconductor.
The inventors previously provided a process of producing a compound semiconductor having a concentration of not more than 0.2 ppmw for the sum of at least one of Fe, Co and Cr and having a resistivity of 10.sup.7 .OMEGA..multidot.cm or more, as described in Japanese Patent Application Publication (Examined) No. Tokuko-hei 5-29,639. In this process, in order to treat a plurality of wafers at the same time, the wafers are aligned at approximately equal intervals in a quartz ampoule by using a jig. InP compound semiconductor wafers which were sliced from a single crystal ingot made by, e.g., the melt growth method using a melt including 0.2 ppmw or less of Fe, Co or Cr; and red phosphorus or the like are placed in the quartz ampoule which is vacuum-sealed. The quartz ampoule is heated at 400-640.degree. C. so that the partial pressure of phosphorus in the ampoule is equal to or higher than a dissociation pressure of InP.
The present inventors further studied from the above-described process to discover that even heat-treating an undoped InP single crystal including a concentration of not more than 0.05 ppmw for the sum of the impurity elements which contain at least one of Fe, Co and Cr failed to semi-insulate the single crystal.
Thereafter, the inventors further studied and provided an improved process of producing a semi-insulating III-V compound semiconductor (InP) having a resistivity of not less than 10.sup.6 .OMEGA..multidot.cm at 300 K and a mobility of above 3,000 cm.sup.2 /V.multidot.s, the semiconductor having a concentration of not more than 0.05 ppmw of all the impurity elements of Fe, Co and Cr, which comprises the steps of placing and vacuum sealing both undoped InP wafers having a concentration of not more than 0.05 ppmw of all the retained impurity of Fe, Co or Cr and a predetermined amount of red phosphorus in a quartz ampoule; and heating the InP wafers under a partial pressure of phosphorus in the ampoule higher than 6 kg/cm.sup.2, as described in Japanese Patent Application Publication (Laid-open) No. Tokukai-hei 3-279,299, "Semi-Insulating InP Single Crystals and Process for Producing the Same".
The improved process aims to suppress deterioration of the mobility caused by the retained impurity and to obtain a mobility higher than a predetermined value, by making the concentration of all the impurity, in particular, the sum of at least one of Fe, Co and Cr, contained in the semi-insulating III-V compound semiconductor (InP)single crystal,not more than 0.05 ppmw. The present inventors further studied the process of the Japanese Patent Application Publication (Laid-open) No. Tokukai-hei 3-279,299. As a result, it is found that according to the above process, although it is possible to obtain an InP single crystal having a higher resistivity and a higher mobility, when a plurality of InP single crystal wafers are simultaneously heat-treated, a wafer which does not have both a high resistivity and a high mobility are often produced, and therefore an InP wafer having both a higher resistivity and a higher mobility is not necessarily and stably obtained.
The inventors further studied and provided a further improved process of producing a semi-insulating InP single crystal, which comprises the steps of; heating an undoped InP single crystal including a retained impurity of at least one of Fe, Co and Cr having a concentration of not more than 0.05 ppmw under a phosphorous vapor pressure in the ampoule higher than 6 kg/cm.sup.2, and thereafter further heating the single crystal at 400-640.degree. C. under a phosphorous vapor pressure in the ampoule not less than a dissociation pressure of InP single crystal, as described in Japanese Patent Application No. Tokugan-hei 6-244,166, "Process for Producing Semi-Insulating InP Single Crystal". The present inventors further studied the process of the Japanese Patent Application No. Tokugan-hei 6-244,166. As a result, it is found that according to the above process, although it is possible to stably obtain an InP single crystal having a higher resistivity and a higher mobility, the InP single crystal obtained by the process does not reach the satisfactory level with respect to the uniformity of resistivity and the uniformity of mobility in the wafer, and therefore the process admits of improvement for the uniformity of electrical properties in the wafer.
The inventors previously reported the results of studies with respect to a heat-treatment in a phosphorous atmosphere with a low phosphorous vapor pressure, i.e., a phosphorous pressure of 1 atm, as shown in "Pro. of 7th Conf. on InP and Related materials, Sapporo. p37-40 (1995)". In the report, although the uniformity of resistivity in the wafer of 24% is shown, the uniformity of resistivity and that of mobility in the wafer will further deteriorate in a heat-treatment on an industrial scale, and therefore the results do not reach the satisfactory level either.
A conventional technique for for obtaining a uniform property in a compound semiconductor single crystal wafer by performing 2 step heat-treatments is disclosed in Japanese Patent Application Publication (Laid-open) No. Tokukai-sho 62-226,900. The technique comprises a first step of heat-treatment at an annealing temperature of 0.85-0.9 times the melting point of the grown crystal, which corresponds to 861-928.degree. C. for InP, and a second step of heat-treatment at an annealing temperature of 0.7-0.75 times the melting point of the grown crystal, which corresponds to 661-728.degree. C. for InP. However, the effect according to the technique is different from that of the present invention because of the difference between the first annealing temperatures. That is, the technique of the Japanese Publication provides a uniform single crystal because the intensity of photo-luminescence is merely stable, and consequently, it is possible to obtain only the effect of good uniformity of various types of properties of the wafer which is produced from the single crystal. The Japanese Publication does not disclose the effects of uniformity of mobility and that of resistivity in the InP single crystal wafer, i.e., of not more than 10%, and of not more than 20%, respectively, which are obtained by the present invention.
Another conventional technique for obtaining a uniform electrical property on the surface of a compound semiconductor single crystal wafer by a heat-treatment is disclosed in Japanese Patent Application Publication (Laid-open) No. Tokukai-hei 2-120,300. The technique comprises the steps of; heat-treating a grown single crystal at 800-1200.degree. C., and thereafter cooling the single crystal to the room temperature with 2-steps of different cooling rates; and therefore is essentially different from the present invention comprising two annealing steps. The effect according to the technique is also different from that of the present invention, that is, the technique enables only considerably uniforming the threshold value of an FET formed on a substrate. The Japanese Publication does not disclose the effects of uniformity of mobility and that of resistivity in the InP single crystal wafer, i.e., of not more than 10%, and of not more than 20%, respectively, which are obtained by the present invention.
Another conventional technique in which two steps of heat-treatments are carried out to a compound semiconductor single crystal wafer is disclosed in Japanese Patent Application Publication (Laid-open) No. Tokukai-hei 2-192,500 by the Applicant. The technique comprises a first step of heat-treatment at an annealing temperature of more than 1100.degree. C. and less than the melting point of the grown single crystal, and a second step of heat-treatment at an annealing temperature of 750-1100.degree. C., in order to obtain a wafer having a small number of micro defects (AB pits) which are generated by an AB-etching. The annealing temperature for the first step heat-treatment in this technique is quite different from that of the present invention and the technique is essentially different from the present invention.
Another conventional heat-treatment technique in which heating and cooling are repeatedly carried out two times or more at temperatures between an upper limit temperature Th which is not less than 800.degree. C. nor more than the melting point of the grown single crystal and a lower limit temperature Tl which is not less than 800.degree. C. nor more than the Th, is disclosed in Japanese Patent Application Publication (Laid-open) No. Tokukai-hei 8-119,800. However, this technique is essentially different from the present invention in that heating and cooling at temperatures between an upper limit temperature Th corresponding to the first step heat-treatment temperature and a lower limit temperature Tl corresponding to the second heat-treatment temperature are repeatedly carried out two times or more. In the present invention, the first step heat-treatment and the subsequent second step heat-treatment are not repeated. The technique is also quite different from the present invention in that the object of the technique is to prevent generation of slip-like defects when an epitaxial growth is carried out by using a wafer sliced from a single crystal ingot to which such a heat-treatment was performed.
R. Fornari et al. reported that as a result of performing heat-treatments two times at 910.degree. C. in a vacuum atmosphere, a semi-insulating InP single crystal (Sample A-S8) having a resistivity of 4.4.times.10.sup.7 .OMEGA..multidot.cm and a mobility of 3940 cm.sup.2 /V.multidot.s was obtained, in "Preparation and characterization of semi-insulating undoped indium phosphide" described in pages 95-100 of Materials Science and Engineering B28 (1994). However, the technique is also quite different from the present invention comprising two steps of heat-treatments under a phosphorous pressure in that heat-treatments of the technique are carried out in a vacuum atmosphere.
G. Hirt et al. reported that as a result of performing a heat-treatment at 900.degree. C., a semi-insulating InP single crystal (annealed VGF Sample) having a resistivity of 1.4.times.10.sup.7 .OMEGA..multidot.cm was obtained, in "Preparation of Homogeneous InP Substrate by VGF-Growth and Wafer Annealing" described in pages 37-40 of Pro. of 7th Conf. on InP and Related Materials, Sapporo (1995). However, the technique is also essentially different from the present invention comprising two steps of heat-treatments.